1. Field of the Invention
This invention relates to write processes for non-volatile memories and particularly to methods of reducing the current required when writing at a high data rate.
2. Description of Related Art
Semiconductor non-volatile memories such as EPROM, EEPROM, and flash memories, which permit electrical erasing and programming of memory cells, are well known. Such memories conventionally include arrays of memory cells where each memory cell includes a floating gate transistor. Write and erase circuits coupled to an array write to or erase a memory cell in the array by electrically charging or discharging the floating gate of the floating transistor in the memory cell to change the threshold voltage of the transistor. In particular, to write to a selected memory cell, the write circuit charges the floating gate of the floating gate transistor in the selected memory cell until the threshold voltage of the transistor is at a level that represents the value being written.
One write method for a non-volatile memory cell uses channel hot electron injection. A typical channel hot electron injection process applies a high voltage (about 12 volts) to the control gate of a floating gate transistor, applies a high voltage (about 5 volts) to the drain of the floating gate transistor, and grounds the source of the floating gate transistor. The high drain-to-source voltage causes a relatively large current through the floating gate transistor. The high control gate voltage attracts energetic (or hot) electrons that can pass from the channel through an insulating layer to the floating gate of the floating gate transistor. As electrons accumulate in the floating gate, the threshold voltage of the floating gate transistor increases, the drain-to-source current falls, and the rate of increase in the threshold voltage drops.
Conventional integrated circuit non-volatile memory currently uses a supply voltage between about 3 volts and about 5 volts. Accordingly, a non-volatile memory using channel hot electron injection for programming typically requires charge pumps to generate the high control gate voltage and the high drain voltage. The sizes of such charge pumps determine the number of memory cells that can be programmed in parallel. In particular, to program N cells in parallel a charge pump must be able to supply N times the current drawn by a single memory cell. At the start of a programming operation, the drain-to-source current through a memory cell being programmed is highest and places the greatest load on the charge pump supplying the drain voltage. Specifically, the charge pump supplies a maximum drain-to-source current Idsmax to each of N memory cells at the start of a parallel programming operation, and the charge pump must be able to supply a total current of N*Idsmax without an unacceptable drop in the drain voltage. If the required programming current could be reduced, a smaller charge pump could be employed which can reduce the overall memory circuit size and cost. Additionally, power consumption could be reduced, which is crucial for portable or battery operated applications.
Another concern in a non-volatile memory that stores an analog value or multiple bits of information in each memory cell is the precision of the write operation. Best precision and repeatability require nearly constant supply and programming voltages during programming. However, as noted above for programming operations, current drain is high at the beginning of the programming operation and falls as a memory cell threshold voltage rises. Accordingly, the charge pumps and the supply voltage in the memory are subject to changing current demands which cause voltage fluctuations or noise that can affect the accuracy and repeatability of write operations. Thus, methods of reducing current consumption, voltage fluctuations, and noise during programming are desired.